Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for forming a side contact in a semiconductor device.
Pattern shrinkage is essential for the improvement of throughput. Pattern shrinkage requires masks to become smaller and smaller. To this end, an argon fluoride (ArF) photoresist (PR) layer has been introduced into the fabrication of semiconductor devices of under 40 nm. However, pattern shrinkage has increased, and the ArF photoresist has reached its limitation as well.
Memory devices, such as Dynamic Random Access Memory (DRAM), require new patterning technology, and accordingly, three-dimensional (3D) cell forming technology is being introduced.
A conventional metal-oxide semiconductor field effect transistor (MOSFET) including planar channels cannot be shrunken even further because the shrinkage of a memory device has come to physical limitations in terms of leakage current, on-current, short-channel effect, and the like. To overcome the problem, researchers are seeking to develop semiconductor devices employing vertical channels.
Semiconductor devices employing vertical channels include channels laid as a perpendicular structure which are formed by forming a pillar-shaped active region extended vertically from a substrate, and a surround-type gate electrode, which is referred to as a vertical gate (VG), surrounding the area around the active region. These semiconductors further include junction regions (i.e., a source region and a drain region) in the upper portion and the lower portion of the active region around the gate electrode. Any one of the junction regions is coupled with a buried bit line (BBL).
FIG. 1 is a cross-sectional view illustrating a semiconductor device having vertical channels according to prior art.
Referring to FIG. 1, a plurality of pillar structures each include a pillar-shaped active region 12, which extends vertically from a substrate 11, and a hard mask layer 13. The external wall of the active region 12 is surrounded by a gate insulation layer 14 and a vertical gate 15. A buried bit line 16 is formed by ion-implanting an impurity into the substrate 11. An interlayer dielectric layer 18 is formed to be buried inside of a trench 17 to separate the buried bit line 16 from a neighboring buried bit line.
Although the conventional semiconductor device employing vertical channels shown in FIG. 1 implants a dopant through ion implantation to form the buried bit line 16, there is a limitation in decreasing the resistance of the buried bit line 16 by implanting a dopant alone when a semiconductor device shrinks. The dopant implantation may deteriorate the characteristics of the semiconductor device if the resistance of the buried bit line 16 is to be decreased in a shrunken semiconductor device.
To overcome the drawback, a technology for decreasing resistance by forming the buried bit line from a metal has been suggested recently. According to the suggested technology, since the buried bit line is a metal layer, an Ohmic-like contact should be achieved between an active region and a buried bit line.
To achieve the Ohmic-like contact, a side contact forming process, which exposes any one sidewall of the active region, is required.
A side contact should be formed on any one sidewall in the lower portion of the active region to couple the active region and the buried bit line, because the height of the buried bit line is low.
However, since the width of the active region is decreased and the depth becomes deeper as a semiconductor device is integrated higher and higher, it is difficult to form a side contact which selectively exposes any one sidewall of an active region. Even if such side contact is formed, there is a limitation in forming the side contact at a uniform depth.